Course structure:

Class 1
DRAM/SRAM/FLASH/MRAM/Emerging memory/...
Class 2
DRAM Design Device – 2hr
Class 3
Front End process- Photo - 2hr
Class 4
Front End process- Dry Etch Process - 2hr
Class 5
Front End process- DIR/TF/CMP/WET/RAM Process –part 1- 2hr
Class 6
Front End process- DIR/TF/CMP/WET/RAM Process –part 2- 2hr
Class 7
Front End process- DIR/TF/CMP/WET/RAM Process –part 3- 2hr
Class 8
SMAI(Smart Manufacturing & AI) (2hrs)
Class 9
Data Science – 2hr
Class 10
Mid-term exam – 2hr
Class 11
Quality Engineering- 2hr
Class 12
Yield rate Engineering - 2hr
Class 13
Backend process- part 1- 2hr
Class 14
Backend process- part 2- 2hr
Class 15
Field Application Engineering -(2 hrs)
Class 16
Final Exam

The detail agendas of each function:
- DRAM Design Device (DEG) -
DRAM Design, Device (DEG)
What's DRAM
DRAM Application
DRAM Architecture
Product Testing

- FE Process -
Photo Process
Dry Etch Process
CMP Process
Thin Film Process
Diffusion Process
WET Process

- SMAI(Smart Manufacturing & AI -
Data engineering challenges in semiconductor data
Machine learning challenges in production
Deep learning for memory array failure classification
Data Science application in photolithography

- YE -
YE: DRAM probing and failure analysis

- Quality –
DRAM Advanced Defect detection and Methodology Application
Machine Learning on Advanced Process Control

- BE Package & Test –
Advanced package introduction - now and future
Memory Packaging Technology Roadmap

- Field Application Engineering –
Field Application Engineering
DRAM Basic Operations and (System) Design Considerations
Market requirements vs. different type of DRAM and trend
Features of DDR4/DDR5/LPDDR4/LPDDR5/GDDR6x
Near Memory, Main Memory and Far Memory
High speed memory design guide and considerations