課程資訊
課程名稱
類比積體電路與系統
Analog Integrated Circuits and Systems 
開課學期
100-2 
授課對象
電機資訊學院  電機工程學研究所  
授課教師
汪重光 
課號
EE4019 
課程識別碼
901 30900 
班次
 
學分
全/半年
半年 
必/選修
選修 
上課時間
星期一5,6,7(12:20~15:10) 
上課地點
電二101 
備註
總人數上限:30人 
 
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課程概述

COURSE OUTLINE (TENTATIVE)

- A. VLSI TECHNOLOGY
2 HRS
- B. OPERATIONAL AMPLIFIERS

2 C. ACTIVE FILTERS

* - D. SAMPLE-AND-HOLD CIRCUITS
1
* - E. DAC/ADC CONVERTERS


1 F. VARIABLE-GAIN/WIDEBAND AMPLIFIERS

2 G. DISTORTION IN AMPLIFIERS AND ITS REDUCTION

1 H. MIXERS/MULTIPLIERS/PHASE DETECTORS

1 I. SIGNAL GENERATORS

* J. POWER AMPLIFIERS

* K. AM AND FM DETECTORS

3 L. CONSTANT MAGNITUDE CONTROL

3 M. FREQUENCY/PHASE LOCK LOOPS
----------------------------------------------
* OPTION 

課程目標
THIS COURSE DEALS WITH THE LINEAR AND NON-LINEAR CIRCUITS, AND ARCHITECTURES IN MIXED ANALOG-DIGITAL VLSI SYSTEMS. AMPLIFIERS,  ADC/DAC, FILTER, MULTIPLIER, OSCILLATOR AND THEIR APPLICATIONS IN SUB-SYSTEMS SUCH AS MAGNITUDE CONTROL AND CLOCK RECOVERY WILL BE COVERED.  
課程要求
PREREQUISITES

LAPLACE TRANSFORM, FREQUENCY-DOMAIN CIRCUIT ANALYSIS; INTRODUCTORY  COURSES IN ELECTRONICS I AND II/III (FAMILIAR WITH PRINCIPLES OF TRANSISTOR OPERATION, AND FUNCTIONING)

ASSIGNMENTS (TENTATIVE)

THERE WILL BE APPROXIMATELY 8 HOMEWORK ASSIGNMENTS.

EXAMS DATES AND GRADING WEIGHTS (TENTATIVE)

PROBLEM SETS: 15%
PROJECT: 15%
MIDTERM: 30% (MIDTERM WEEK SCHEDULED BY UNIVERSITY)
FINAL: 40% (FINAL WEEK SCHEDULED BY UNIVERSITY)
 
預期每週課後學習時數
 
Office Hours
 
參考書目
TEXTBOOK: "PHASE-LOCKED LOOPS - DESIGN, SIMULATION, AND APPLICATIONS", ROLAND E. BEST, 5TH. EDITION, THE MCGRAW-HILL, NEW YORK, 2003

 
指定閱讀
 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
無資料