課程資訊

SWITCHING CIRCUIT AND LOGIC DESIGN

98-1

EE2012

901 32300

01

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/981logic

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 20 Circuits for Arithmetic Operations

Office Hours

C. H. Roth, Jr. Fundamentals of Logic Design, 5th edition, Thomson. 2003

(僅供參考)

 No. 項目 百分比 說明 1. Participation 2% 2. 作業 17% 3. 隨堂測驗 11% 4. 期末考 35% 5. 期中考 35%

 課程進度
 週次 日期 單元主題 第1週 Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra 第1週 Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra 第2週 Ch 2 Boolean AlgebraCh 3 Boolean Algebra (cont’d) 第3週 Ch 4 Application of Boolean Algebra 第4週 Ch 5 Karnaugh Maps 第5週 Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第6週 Quiz 1 Ch 8 Combinational Ckt Design (skip 8.1, 8.2) 第7週 Ch 8 (cont’d) Ch 9 Multiplexers Decoders and PLD (skip 9.7) 第8週 Ch 9 (cont’d) Verilog: Combinational Circuits (3:30-6:00pm) 第9週 Midterm 第10週 Ch 11 Latches and FF 第11週 Ch 12 Registers and Counters 第12週 Ch 13 Analysis of Clock Sequential Ckts 第13週 Ch 14 Derivation of State Graphs and Tables ( Skip examples 2 and 3 in Sec. 14.3) 第14週 Quiz 2 Ch 15 Reduction of State Tables (15.1, 15.2) 第15週 Ch 16 Sequential Ckt Design (16.1 to 16.4) 第16週 Ch 18 Circuits for Arithmetic Op. (18.1-18.2) 1/1 元旦放假一天 第17週 Supplementary materials