課程資訊
課程名稱
交換電路與邏輯設計
Switching Circuit and Logic Design 
開課學期
110-1 
授課對象
電機工程學系  
授課教師
吳安宇 
課號
EE2012 
課程識別碼
901 32300 
班次
01 
學分
3.0 
全/半年
半年 
必/選修
必修 
上課時間
星期四8(15:30~16:20)星期五8,9(15:30~17:20) 
上課地點
博理113博理113 
備註
本系優先
總人數上限:80人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1101_LD 
課程簡介影片
 
核心能力關聯
核心能力與課程規劃關聯圖
課程大綱
為確保您我的權利,請尊重智慧財產權及不得非法影印
課程概述

SCHEDULE (TENTATIVE)
WEEK TOPIC COMMENT
1 CH 1 INTRODUCTION: NUMBER SYSTEMS
中秋節放假

2 CH 1 INTRODUCTION: NUMBER SYSTEMS (CONT’D)
CH 2 BOOLEAN ALGEBRA

3 CH 3 BOOLEAN ALGEBRA (CONT’D)

4 QUIZ 1
CH 4 APPLICATION OF BOOLEAN ALGEBRA

5 國慶日放假

6 CH 5 KARNAUGH MAPS
CH 7 MULTI-LEVEL GATE CIRCUITS; NAND NOR GATES

7 QUIZ 2
CH 8 COMBINATIONAL CKT DESIGN

8 CH 9 MULTIPLEXERS DECODERS AND PLD

9 MIDTERM

10 CH 11 LATCHES AND FF
校慶

11 CH 11 LATCHES AND FF (CONT'D)
CH 12 REGISTERS AND COUNTERS
QUARTUS II

12 CH 12 REGISTERS AND COUNTERS (CONT'D)
CH 13 ANALYSIS OF CLOCK SEQUENTIAL CKTS

13 QUIZ 3
QUARTUS II

14 CH 13 ANALYSIS OF CLOCK SEQUENTIAL CKTS (CONT'D)
CH 14 DERIVATION OF STATE GRAPHS AND TABLES

15 CH 14 DERIVATION OF STATE GRAPHS AND TABLES (CONT'D)
CH 15 REDUCTION OF STATE TABLES (15.1 TO 15.3)

16 QUIZ 4
CH 16 SEQUENTIAL CKT DESIGN (16.1 TO 16.4)

17 CH 16 SEQUENTIAL CKT DESIGN (16.1 TO 16.4) (CONT'D)

18 FINAL EXAM 

課程目標
待補 
課程要求
GRADING : TO BE ANNOUNCED

ABOUT VERILOG AND LAB :
- TA GIVES A DETAILED VERILOG LECTURE (2.5 HOURS, COMBINATIONAL CIRCUITS IN GATE-LEVEL NETLIST DESCRIPTION ONLY).
- TA GIVES A DEMO ABOUT HOW TO USE THE VERILOG SIMULATOR IN CLASS. THE SIMULATOR IS VERILOG-XL AND DEBUSSY. (XWINDOW, XMING, PUTTY, EDITOR)
- TA WRITES A STEP-BY-STEP LAB INSTRUCTION TO TEACH STUDENTS HOW TO WRITE AN ADDER IN GATE-LEVEL NETLIST.
- AFTER THE LECTURE, TA RESERVES FOUR TIME SLOTS (6:00-8:30 PM) IN THE PC CLASSROOM FOR STUDENTS TO PRACTICE THE LAB BY THEMSELVES. ASK 1-2 SIMPLE QUESTIONS ABOUT THE LAB AND ASK STUDENTS TO SUBMIT THE ANSWERS ALONG WITH HW4.
- TA GIVE 5% BONUS PROBLEM IN THE FINAL EXAM. 
預期每週課後學習時數
 
Office Hours
 
參考書目
教科書: Textbook
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition,
CENGAGE Learning. 
指定閱讀
待補 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
第1週
9/23,9/24  9/23: Course Overview (線上說明)- Ch 1 Intro, Number Systems (請在9/23前 先線上完成預習 NTU COOL)9/24: - Ch 2 Boolean Algebra (線上上課) 
第2週
9/30,10/01  - Ch 3 Boolean Algebra (Continued) (線上上課)
- Ch 4 Applications of Boolean Algebra (同步 錄影播放)
 
第3週
10/07,10/08  - Ch 4 Applications of Boolean Algebra (線上上課)
- Ch 5 Karnaugh Maps (線上上課)


Dear all,

After discussing with my PhD students, they think a format of hybrid learning would be good to you. But we still need to do some "experiments" on this new format before Week 4.

1. Don't forget to attend the first Quiz (6%) on 10/14.
 
第4週
10/14,10/15  10/14: 第一次 Quiz 1 (Ch 1-3)
10/15:
- Ch 5 Karnaugh Maps (請預習)
- Overview of Ch. 3, 4, 5 (實體上課)
 
第5週
10/21,10/22  - Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 
第6週
10/28,10/29  10/28: Quiz 2 (Ch 4-5) 6% 3:30pm-4:30pm (座位另外由大助教公布)

10/29 (觀看 COOL videos) (吳老師請假 - 無實體上課)

- Ch 8 Combinational Ckt Design
- Ch 9 Multiplexers Decoders (Part-I)


 
第7週
11/04,11/05  1. 做 Zuvio課堂測驗

2. Ch 9 Multiplexers Decoders and PLDs, and Shannon's expansion
 
第8週
11/11,11/12  - Ch 11 Latches and FFs (video in COOL)
- Midterm (Ch1-5, 7-9) 
第9週
11/18,11/19  - Ch 11 Latches and FFs
- Ch 12 Registers and Counters 
第10週
11/25,11/26  11/25 - Ch 13 Analysis of Clocked Sequential Ckts

11/26 - TA Hour: Combinational Circuit Design using Altera Quartus II  
第11週
12/02,12/03  12/02- Ch 14 Derivation of State Graphs and Table12/03 No Class (NTU Anniversary)  
第12週
12/09,12/10  - Ch 14 Derivation of State Graphs and Table
- Ch 15 Reduction of State Tables (12/9)

12/10: TA hour 
第13週
12/16,12/17  - Quiz 3 (Ch 11-13)
- Ch 15 Reduction of State Tables
- Ch 16 Sequential Ckt Design 
第14週
12/23,12/24  CH18 Arithmetic Operations 2020-1-7 v1
 
第15週
12/30,12/31  - Ch 16 Sequential Ckt Design (No class)
- No Class on 12/31 (New Year’s Day) 
第16週
1/06,1/07  - Review Session
- Final Exam (Ch 11-16) 
第17週
1/13,1/14  - Supplementary Material (FPGA)
- TA Hour: Sequential Circuit Design using Altera Quartus II  
第18週
1/20,1/21  - Supplementary Material: What's next beyond SCLD? (1/20 in BL-113)

- From SCLD to VLSI Design (later in COOL)