課程資訊
課程名稱
交換電路與邏輯設計
Switching Circuit and Logic Design 
開課學期
111-1 
授課對象
電機工程學系  
授課教師
吳安宇 
課號
EE2012 
課程識別碼
901 32300 
班次
01 
學分
3.0 
全/半年
半年 
必/選修
必修 
上課時間
星期四8(15:30~16:20)星期五8,9(15:30~17:20) 
上課地點
博理113博理113 
備註
外系學生加選請於加退選時詢問授課老師,
限本系所學生(含輔系、雙修生)
總人數上限:80人 
 
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課程概述

SCHEDULE (TENTATIVE)
WEEK TOPIC COMMENT
1 CH 1 INTRODUCTION: NUMBER SYSTEMS AND CONV.
CH 2 BOOLEAN ALGEBRA

2 CH 2 BOOLEAN ALGEBRA
CH 3 BOOLEAN ALGEBRA (CONT’D) HW1 ASSIGNED

3 CH 4 APPLICATION OF BOOLEAN ALGEBRA

4 CH 5 KARNAUGH MAPS
HW2 ASSIGNED

5 CH 7 MULTI-LEVEL GATE CIRCUITS; NAND NOR GATES

6 QUIZ 1
CH 8 COMBINATIONAL CKT DESIGN (SKIP 8.1, 8.2)

7 CH 8 (CONT’D)
CH 9 MULTIPLEXERS DECODERS AND PLD (SKIP 9.7) HW3 ASSIGNED

8 CH 9 (CONT’D)
VERILOG: COMBINATIONAL CIRCUITS (3:30-6:00PM)

9 NO CLASS
MIDTERM

10 CH 11 LATCHES AND FF

11 CH 12 REGISTERS AND COUNTERS HW4 ASSIGNED + LAB QUESTIONS

12 CH 13 ANALYSIS OF CLOCK SEQUENTIAL CKTS

13 CH 14 DERIVATION OF STATE GRAPHS AND TABLES
( SKIP EXAMPLES 2 AND 3 IN SEC. 14.3) HW5 ASSIGNED

14 QUIZ 2
CH 15 REDUCTION OF STATE TABLES (15.1 TO 15.2) QUIZ2 1 HOUR
LECTURE 2 HOURS

15 CH 16 SEQUENTIAL CKT DESIGN (16.1 TO 16.4)

16 CH 18 CIRCUITS FOR ARITHMETIC OP. (18.1-18.2)
1/1 元旦放假一天 HW6 ASSIGNED

17 SUPPLEMENTARY MATERIALS

18 FINAL EXAM 

課程目標
OBJECTIVE: LEARN BASIC BOOLEAN ALGEBRA AND LOGIC DESIGN SKILLS AND FLOW. PAVE THE WAY FOR COMPUTER ARITHMETIC (ADDER, MULTIPLIER, ETC.) AND/OR ARITHMETIC/LOGIC UNIT (ALU) DESIGN OF CPU IN COMPUTER SYSTEMS. 
課程要求
GRADING : TO BE ANNOUNCED

ABOUT VERILOG AND LAB :
- TA GIVES A DETAILED VERILOG LECTURE (2.5 HOURS, COMBINATIONAL CIRCUITS IN GATE-LEVEL NETLIST DESCRIPTION ONLY).
- TA GIVES A DEMO ABOUT HOW TO USE THE VERILOG SIMULATOR IN CLASS. THE SIMULATOR IS VERILOG-XL AND DEBUSSY. (XWINDOW, XMING, PUTTY, EDITOR)
- TA WRITES A STEP-BY-STEP LAB INSTRUCTION TO TEACH STUDENTS HOW TO WRITE AN ADDER IN GATE-LEVEL NETLIST.
- AFTER THE LECTURE, TA RESERVES FOUR TIME SLOTS (6:00-8:30 PM) IN THE PC CLASSROOM FOR STUDENTS TO PRACTICE THE LAB BY THEMSELVES. ASK 1-2 SIMPLE QUESTIONS ABOUT THE LAB AND ASK STUDENTS TO SUBMIT THE ANSWERS ALONG WITH HW4.
- TA GIVE 5% BONUS PROBLEM IN THE FINAL EXAM. 
預期每週課後學習時數
 
Office Hours
 
參考書目
TEXTBOOK

CHARLES. H. ROTH, JR. & LARRY L. KINNEY, FUNDAMENTALS OF LOGIC DESIGN, 6TH EDITION, CENGAGE LEARNING, 2010.




REFERENCE VERILOG TEXTBOOK (NOT REQUIRED) :
1. (MAJOR VERILOG CODING REFERENCE TEXTBOOK) “VERILOG HDL: DIGITAL DESIGN AND MODELING,” JOSEPH CAVANAGH, CRC PRESS, 2007.
2. (基礎)“DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS," MING-BO LIN, WILEY, 2008. 
指定閱讀
 
評量方式
(僅供參考)
   
課程進度
週次
日期
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