課程資訊

Switching Circuit and Logic Design

102-1

EE2012

901 32300

01

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1021logic_design

「交換電路與邏輯設計」課程將介紹如何以「開關」(switch)作為實現布林邏輯與設計數位電路之基本元件，並介紹如何有系統地優化交換電路(switching circuit)。

Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations
Hardware Description Language: Verilog (basics)

Office Hours

Charles. H. Roth, Jr. & Larry L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning, 2013.

1. (Major Verilog coding reference textbook) “Verilog HDL: Digital design and modeling,” Joseph Cavanagh, CRC Press, 2007.
2. (基礎)“Digital system designs and practices: Using Verilog HDL and FPGAs," Ming-Bo Lin, Wiley, 2008.

(僅供參考)

 No. 項目 百分比 說明 1. Homework 18% 2. Quiz1 4% 3. Midterm 35% 4. Quiz2 6% 5. Final 35% 6. Participation 2%

 課程進度
 週次 日期 單元主題 第1週 9/12,9/13 Homework1
Ch 2 Boolean Algebra
Ch 1 Introduction: Number Systems and Conv
Ch 0 Course Overview
2013 Logic Design Syllabus

Ch4 Application of Boolean Algebra
Ch3 Boolean Algebra (continued)

Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第6週 10/17,10/18 Quiz 1 (ch1 - ch4)
Advanced: Introduction of Verilog 第7週 10/24,10/25 Advanced: Introduction of Wallace Tree Multiplication
Ch8 Combinational Ckt Design
Ch9 Multipliexers Decoders and PLD (skip 9.7) 第8週 10/31,11/01 Ch11 Latches and FF
Advanced: LAB Exercise 第9週 11/07,11/08 Midterm (Ch1 - Ch9) 第10週 11/14,11/15 Ch 11 Latches and FF 第11週 11/21,11/22 Ch 12 Registers and Counters 第12週 11/28,11/29 Ch 13 Analysis of Clock Sequential Ckts Homework 5 第13週 12/05,12/06 Ch 14 Derivation of State Graphs and Tables
Homework6 第14週 12/12,12/13 Quiz 2
Ch 15 Reduction of State Tables (15.1 to 15.2) 第15週 12/19,12/20 Advanced: Introduction of final project
Ch 16 Sequential Ckt Design (16.1 to 16.4)
Homework7 第16週 12/26,12/27 Ch 16 (cont’d)
Ch 18 Circuits for Arithmetic Op. (18.1-18.2)
project_alu_supplement.pdf 第17週 1/02,1/03 Ch 18 (cont’d)
Advanced: Presentation 第18週 1/2,1/3 Final exam