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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
108-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
吳安宇 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
01 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四8(15:30~16:20)星期五8,9(15:30~17:20) |
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上課地點 |
博理113博理113 |
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備註 |
本系優先
總人數上限：60人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1081_LD |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
SCHEDULE (TENTATIVE)
WEEK TOPIC COMMENT
1 CH 1 INTRODUCTION: NUMBER SYSTEMS
中秋節放假
2 CH 1 INTRODUCTION: NUMBER SYSTEMS (CONT’D)
CH 2 BOOLEAN ALGEBRA
3 CH 3 BOOLEAN ALGEBRA (CONT’D)
4 QUIZ 1
CH 4 APPLICATION OF BOOLEAN ALGEBRA
5 國慶日放假
6 CH 5 KARNAUGH MAPS
CH 7 MULTI-LEVEL GATE CIRCUITS; NAND NOR GATES
7 QUIZ 2
CH 8 COMBINATIONAL CKT DESIGN
8 CH 9 MULTIPLEXERS DECODERS AND PLD
9 MIDTERM
10 CH 11 LATCHES AND FF
校慶
11 CH 11 LATCHES AND FF (CONT'D)
CH 12 REGISTERS AND COUNTERS
QUARTUS II
12 CH 12 REGISTERS AND COUNTERS (CONT'D)
CH 13 ANALYSIS OF CLOCK SEQUENTIAL CKTS
13 QUIZ 3
QUARTUS II
14 CH 13 ANALYSIS OF CLOCK SEQUENTIAL CKTS (CONT'D)
CH 14 DERIVATION OF STATE GRAPHS AND TABLES
15 CH 14 DERIVATION OF STATE GRAPHS AND TABLES (CONT'D)
CH 15 REDUCTION OF STATE TABLES (15.1 TO 15.3)
16 QUIZ 4
CH 16 SEQUENTIAL CKT DESIGN (16.1 TO 16.4)
17 CH 16 SEQUENTIAL CKT DESIGN (16.1 TO 16.4) (CONT'D)
18 FINAL EXAM |
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課程目標 |
待補 |
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課程要求 |
GRADING : TO BE ANNOUNCED
ABOUT VERILOG AND LAB :
- TA GIVES A DETAILED VERILOG LECTURE (2.5 HOURS, COMBINATIONAL CIRCUITS IN GATE-LEVEL NETLIST DESCRIPTION ONLY).
- TA GIVES A DEMO ABOUT HOW TO USE THE VERILOG SIMULATOR IN CLASS. THE SIMULATOR IS VERILOG-XL AND DEBUSSY. (XWINDOW, XMING, PUTTY, EDITOR)
- TA WRITES A STEP-BY-STEP LAB INSTRUCTION TO TEACH STUDENTS HOW TO WRITE AN ADDER IN GATE-LEVEL NETLIST.
- AFTER THE LECTURE, TA RESERVES FOUR TIME SLOTS (6:00-8:30 PM) IN THE PC CLASSROOM FOR STUDENTS TO PRACTICE THE LAB BY THEMSELVES. ASK 1-2 SIMPLE QUESTIONS ABOUT THE LAB AND ASK STUDENTS TO SUBMIT THE ANSWERS ALONG WITH HW4.
- TA GIVE 5% BONUS PROBLEM IN THE FINAL EXAM. |
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預期每週課後學習時數 |
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Office Hours |
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參考書目 |
教科書： Textbook
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition,
CENGAGE Learning. |
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指定閱讀 |
待補 |
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評量方式
(僅供參考) |
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週次 |
日期 |
單元主題 |
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第1週 |
9/12,9/13 |
Ch 1 Intro, Number Systems |
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第2週 |
9/19,9/20 |
Ch 1 (cont’d)
Ch 2 Boolean Algebra |
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第3週 |
9/26,9/27 |
Ch 2 (updated slide)
Ch 3 Boolean Algebra (cont'd)
Both files are cryto-coded |
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第4週 |
10/03,10/04 |
Quiz 1 (Ch1-3)
Ch 4 Applications of Boolean Algebra - Friday
Ch 5 Karnaugh Maps - Saturday |
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第5週 |
10/10,10/11 |
The National Day (國慶日) |
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第6週 |
10/17,10/18 |
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates
CH 8 Combinational Circuits Design |
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第7週 |
10/24,10/25 |
Quiz 2 (Ch4, 5)
Ch 8 Combinational Ckt Design (skip Fig 8-12, 8-14) |
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第8週 |
10/31,11/01 |
Ch 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8, and Shannon’s expansion (eqs. 9-10~12) will be included in the exam.) |
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第9週 |
11/07,11/08 |
Midterm (Ch1-5, 7-9) |
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第10週 |
11/14,11/15 |
Ch 11 Latches and FFs
11/14: Chapter 11
11/15: No class due to NTU Anniversity |
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第11週 |
11/21,11/22 |
11/21: Ch 12 Registers and Counters
11/22: Combinational Circuit Design using Altera Quartus II
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第12週 |
11/28,11/29 |
Ch 12 (cont’d)
Ch 13 Analysis of Clocked Sequential Ckts |
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第13週 |
12/05,12/06 |
Ch 13 (cont’d)
Ch 14 Derivation of State Graphs and Tables ( Skip Examples 2 & 3 in Sec. 14.3)
Ch 15 Reduction of State Tables (15.1 to 15.3) |
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第14週 |
12/12,12/13 |
Quiz 3 (Ch11-12)
Sequential Circuit Design using Altera Quartus II |
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第15週 |
12/19,12/20 |
CH 15 Reduction of State Tables (cont'd)
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
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第16週 |
12/26,12/27 |
Quiz 4 (Ch13-14)
Ch 16 Sequential Ckt Design (16.1 to 16.4)
Ch 18 Arithmetic Operations |
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第17週 |
1/02,1/03 |
1/2: Extension of Logic Design (0.5% of grade)
1/3: No class |
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第18週 |
1/09, 1/10 |
1/9 Office hour
1/10 Final Exam (Ch 11-16) |
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