課程資訊

Switching Circuit and Logic Design

101-1

EE2012

901 32300

01

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1011_logic_wu

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 20 Circuits for Arithmetic Operations

•1 運用數學、科學及工程知識的能力。

•2 設計與執行實驗，以及分析與解釋數據的能力。

•3 執行工程實務所需技術、技巧及使用工具之能力。

•4 設計工程系統、元件或製程之能力。

Raw Score 原始分數
HW 18%, Quiz1 4%, Midterm 35%, Quiz2 6%
Final 35%, Participation 2%

Final letter grade依分佈等第給分(A+: within top 8% among the total student body of four classes in whole)

Office Hours

Charles. H. Roth, Jr. & Larry L. Kinney, Fundamentals of Logic Design, 6th
edition, CENGAGE Learning, 2010. (International Edition)

1. (Major Verilog coding reference textbook) “Verilog HDL: Digital design and
modeling,” Joseph Cavanagh, CRC Press, 2007.
2. (基礎)“Digital system designs and practices: Using Verilog HDL and FPGAs,"
Ming-Bo Lin, Wiley, 2008.

C. H. Roth, Jr. Fundamentals of Logic Design, 6th edition, Thomson. 2010 (International Edition)

(僅供參考)

 No. 項目 百分比 說明 1. 請看 課程要求 100%

 課程進度
 週次 日期 單元主題 第1週 9/13,9/14 < Ch 1 Introduction: Number Systems and Conv > < Ch 2 Boolean Algebra > 第2週 9/20(1:20pm 補課),9/21 < Ch 2 Boolean Algebra > < Ch 3 Boolean Algebra (cont’d) > < Ch 4 Application of Boolean Algebra > 第3週 9/27(1:20pm 補課),9/28 < Ch 4 Application of Boolean Algebra > < Ch 5 Karnaugh Maps > 第4週 10/04(1:20pm 補課),10/05 < Ch 5 Karnaugh Maps > < Ch 7 Multi-Level Gate Circuits; NAND NOR Gates > 第5週 10/11,10/12 TA Time 第6週 10/18,10/19 < Quiz 1 (Ch 1-5) > < 10/19 放假 > 第7週 10/25(1:20pm 補課),10/26 < Ch 8 (cont’d) > < Ch 9 Multiplexers Decoders and PLD (skip 9.7) > 第8週 11/01(1:20pm 補課),11/02 < Ch 9 (cont’d) > < Verilog: Combinational Circuits (3:30-6:00pm) > 第9週 11/08,11/09 < No class > < Midterm > 第10週 11/15,11/16 < 校慶 > < Ch 11 Latches and FF > 第11週 11/22,11/23 < Ch 12 Registers and Counters > 第12週 11/29,11/30 < Ch 13 Analysis of Clock Sequential Ckts > 第13週 12/06,12/07 < Ch 14 Derivation of State Graphs and Tables (Skip examples 2 and 3 in Sec. 14.3) > < Ch 15 Reduction of State Tables (15.1 to 15.2) > 第14週 12/13,12/14 < Quiz 2 (Ch 11-13) > < Ch 15 Reduction of State Tables (15.1 to 15.2) > 第15週 12/20,12/21 < Ch 16 Sequential Ckt Design (16.1 to 16.4) > 第16週 12/27,12/28 < Ch 18 Circuits for Arithmetic Op. (18.1-18.2) > 第17週 1/03,1/04 < Supplementary materials > 第18週 1/10,1/11 < No class > < Final exam >