課程資訊

Switching Circuit and Logic Design

102-1

EE2012

901 32300

02

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1021Logic

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 18 Circuits for Arithmetic Operations

•1 運用數學、科學及工程知識的能力。

•2 設計與執行實驗，以及分析與解釋數據的能力。

•3 執行工程實務所需技術、技巧及使用工具之能力。

•4 設計工程系統、元件或製程之能力。

Office Hours

TEXTBOOK
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning.

(僅供參考)

 No. 項目 百分比 說明 1. HW 18% 2. Quiz 1 4% 3. Midterm 35% 4. Quiz 2 6% 5. Final 35% 6. Participation 2% 7. 學期總成績 100% Final letter grade依分佈等第給分(A+: within top 8% among the total student body of four classes in whole)

 課程進度
 週次 日期 單元主題 第1週 9/12,9/13 Ch 1 Introduction: Number Systems and Conv. Ch 2 Boolean Algebra 第2週 9/19,9/20 中秋連假 第3週 9/26,9/27 Ch 2 Boolean Algebra Ch 3 Boolean Algebra (continued) Ch 4 Application of Boolean Algebra 第4週 10/03,10/04 Ch 4 Application of Boolean Algebra Ch 5 Karnaugh Maps 第5週 10/10,10/11 雙十國慶 Ch 5 Karnaugh Maps Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第6週 10/17,10/18 Quiz 1 (Ch 1-4) Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第7週 10/24,10/25 Ch 8 Combinational Ckt Design (skip 8.1, 8.2) Ch 9 Multiplexers Decoders and PLD (skip 9.7) 第8週 10/31,11/01 Ch 9 Multiplexers Decoders and PLD (skip 9.7) Verilog: Combinational Circuits (15:30-18:00) 第9週 11/07,11/08 No class Midterm (Ch1-9) 第10週 11/14,11/15 Ch 11 Latches and FF 校慶 第11週 11/21,11/22 Ch 11 Latches and FF Ch 12 Registers and Counters 第12週 11/28,11/29 Ch 12 Registers and Counters Ch 13 Analysis of Clock Sequential Ckts 第13週 12/05,12/06 Ch 13 Analysis of Clock Sequential Ckts Ch 14 Derivation of State Graphs and Tables ( Skip examples 2 and 3 in Sec. 14.3) 第14週 12/12,12/13 Quiz 2 (Ch 11-13) Ch 14 Derivation of State Graphs and Tables ( Skip examples 2 and 3 in Sec. 14.3) Ch 15 Reduction of State Tables (15.1 to 15.2) 第15週 12/19,12/20 Ch 15 Reduction of State Tables (15.1 to 15.2) Ch 16 Sequential Ckt Design (16.1 to 16.4) 第16週 12/26,12/27 Ch 16 Sequential Ckt Design (16.1 to 16.4) Ch 18 Circuits for Arithmetic Op. (18.1-18.2) 第17週 1/02,1/03 Ch 18 Circuits for Arithmetic Op. (18.1-18.2) Supplementary materials