課程資訊

Switching Circuit and Logic Design

103-1

EE2012

901 32300

02

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1031logic

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 18 Circuits for Arithmetic Operations

•1 運用數學、科學及工程知識的能力。

•2 設計與執行實驗，以及分析與解釋數據的能力。

•3 執行工程實務所需技術、技巧及使用工具之能力。

•4 設計工程系統、元件或製程之能力。

Office Hours

TEXTBOOK
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning.

(僅供參考)

 No. 項目 百分比 說明 1. HW 14% 2. Quiz 1 4% 3. Midterm 35% 4. Quiz 2 4% 5. Project 6% 6. Final 35% 7. Participation 2% 8. 學期總成績 100% Final letter grade依分佈等第給分(A+: within top 8% among the total student body of four classes in whole)

 課程進度
 週次 日期 單元主題 第1週 09/18, 09/19 Ch 1 Number Systems and Conversion
Ch 2 Boolean Algebra 第2週 09/25, 09/26 Ch 2 Boolean Algebra
Ch 3 Boolean Algebra (Continued) 第3週 10/02, 10/03 Ch 4 Applications of Boolean Algebra 第4週 10/09 Ch 5 Karnaugh Map 第5週 10/16, 10/17 Ch 5 Karnaugh Maps
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第6週 10/23, 10/24 Quiz 1 (Ch 1-4)
Ch 8 Combinational Ckt Design (skip 8.1, 8.2) 第7週 10/30, 10/31 Ch 8 Combinational Ckt Design (skip 8.1, 8.2)
Ch 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8) 第8週 11/06 , 11/07 Ch 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8)
Combinational Circuit Design using Altera Quartus II; Verilog Basics 第9週 11/13, 11/14 Review Session
Midterm (Ch1-9) 第10週 11/20, 11/21 Ch 11 Latches and FFs 第11週 11/27, 11/28 Ch 12 Registers and Counters 第12週 12/04, 12/05 Ch 13 Analysis of Clocked Sequential Ckts 第13週 12/11, 12/12 Ch 14 Derivation of State Graphs and Tables ( Skip Examples 2 & 3 in Sec. 14.3)
Ch 15 Reduction of State Tables (15.1 to 15.2) 第14週 12/18, 12/19 Quiz 2 (Ch 11-13)
Sequential Circuit Design using Altera Quartus II; Verilog Basics 第15週 12/25, 12/26 Ch 16 Sequential Ckt Design (16.1 to 16.4) 第16週 01/01, 01/02 Holiday
Help Session 第17週 01/08, 01/09 Presentation of Selected Projects
Supplementary materials 第18週 01/15, 01/16 Review Session
Final exam