課程資訊

Switching Circuit and Logic Design

102-1

EE2012

901 32300

03

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1021LD_cmli

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 20 Circuits for Arithmetic Operations

HW
Quiz1
Midterm
Quiz2
Final
Participation

Office Hours

(僅供參考)

 No. 項目 百分比 說明 1. Midterm 35% 2. Final 35% 3. quiz 1 4% 4. quiz2 6% 5. Homework 18% 6. participation 2%

 課程進度
 週次 日期 單元主題 第1週 Course Info./ CH1 Introduction 第2週 中秋 第3週 Ch2 / Ch 3 Boolean Algebra (9/25 updated) 第4週 Ch 4 Application of Boolean Algebra (Th 13:20) 第5週 Ch 5 Karnaugh Maps 第6週 10/17 QUIZ#1 (Th 14:20); Ch 7 Multi-Level Gate Circuits 第7週 Ch 8 Comb. Ckt Design (Th 13:20) 第8週 Ch 9 Multiplexers Decoders and PLD (Th13:20); Verilog (F) 3:30-6:00pm 第9週 no class(Th); midterm (F) 第10週 CH 11 Lastes and FF (Th 13:20); 校慶(F) 第11週 老師參加國際會議 no class 第12週 CH 12 Registers (Th 13:20) 第13週 CH 13 Analysis of Seq. Ckt (Th 13:20); Ch 14 Derivation of State Graphs and Tables 第14週 12/12 Quiz #2(Th 14:20); Ch 15 Reduction of State Tables 第15週 12/19 Ch 16 Sequential Ckt Design (Th 13:20) 第16週 12/26 Ch 18 Circuit for Arithmetic Operation (Th 13:20) 第17週 Quine-Mucluskey + review 第18週 Fianl exam (F)