課程資訊

Switching Circuit and Logic Design

110-1

EE2012

901 32300

03

3.0

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1101SCLD_03

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 11 Latches and FFs
11. Unit 12 Registers and Counters
12. Unit 13 Analysis of Clocked Sequential Circuits
13. Unit 14 Derivation of State Graphs and Tables
14. Unit 15 Reduction of State Tables-- State assignment
15. Unit 16 Sequential Circuit Design

Basic knowledges in Switching Circuits and Logic Design

Quiz 1~3, Quartus II assignment 1 & 2, Midterm, Final, Participation
**Final letter grade is given according to distribution. (A+: within top 8% among the total student body of four classes in whole.)
**Copying someone else’s homework/test or part of a homework/test is cheating. When cheating is discovered, all students involved will receive no credit for the homework/test.

Office Hours

C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning.

(僅供參考)

 No. 項目 百分比 說明 1. Quiz 18% Quiz 1~3 2. Quartus II 10% Quartus II Assignment 1~2 3. Midterm 35% 4. Final 35% 5. Participation 2%

 課程進度
 週次 日期 單元主題 第1-1週 9/23 Ch 1 Number Systems [Online] 線上同步課程：每週四的連結如下 https://ntucc.webex.com/ntucc/j.php?MTID=m0e808b1585306d9bce27fdf994ff11bd 第1-2週 9/24 Ch 2 Boolean Algebra [Online] 線上同步課程：每週五的連結如下 https://ntucc.webex.com/ntucc/j.php?MTID=mccbaa9e4522d13a0eb8ea521426f625f 第2-1週 9/30 Ch 2 Boolean Algebra [Online] 第2-2週 10/01 Ch 3 Boolean Algebra (Continued) [Online] 第3-1週 10/07 Ch 3 Boolean Algebra (Continued) [Online] 第3-2週 10/08 Ch 4 Applications of Boolean Algebra {Skip Carry Lookahead Adder in 4.7} [Online] 第4-1週 10/14 Quiz 1 (Ch 1-3) 第4-2週 10/15 Ch 5 Karnaugh Map 第5-1週 10/21 Ch 7 Multi-Level Gate Circuits; NAND NOR Gates 第5-2週 10/22 Ch 7 Multi-Level Gate Circuits; NAND NOR Gates; Ch 8 Combinational Ckt Design {Skip Figs. 8-12, 8-14} 第6-1週 10/28 Quiz 2 (Ch 4-5) 第6-2週 10/29 Ch 8 Combinational Ckt Design Ch 9 Multiplexers Decoders and PLDs {Skip PAL in 9.6, 9.7, 9.8, but include PLA as well as Shannon's expansion Eqs. 9-10~12} 第7-1週 11/04 Ch 9 Multiplexers Decoders and PLDs 第7-2週 11/05 CH 11 Latches and FFs {Combinational Circuit Design using Altera Quartus II (TA Lecture) [online]} 第8-1週 11/11 Review Session 第8-2週 11/12 Midterm (Ch 1-5, 7-9) 第9-1週 11/18 CH 11 Latches and FFs {Skip 11.9} 第9-2週 11/19 Ch 12 Registers and Counters 第10-1週 11/25 Ch 12 Registers and Counters 第10-2週 11/26 Combinational Circuit Design using Altera Quartus II (TA Hour) 第11-1週 12/02 Ch 12 Registers and Counters; Ch 13 Analysis of Clocked Sequential Ckts {Quartus II HW1 Due} 第11-2週 12/03 NTU Anniversary, No Class 第12-1週 12/09 Ch 13 Analysis of Clocked Sequential Ckts 第12-2週 12/10 Ch 13 Analysis of Clocked Sequential Ckts 第13-1週 12/16 Quiz 3 (Ch 11-13) 第13-2週 12/17 Ch 14 Derivation of State Graphs and Tables {Skip Examples 2 and 3 in 14.3} {Sequential Circuit Design using Altera Quartus II (TA Lecture) [online]} 第14-1週 12/23 Ch 14 Derivation of State Graphs and Tables 第14-2週 12/24 Ch 15 Reduction of State Tables (15.1 to 15.3) Ch 16 Sequential Ckt Design (16.1 to 16.4) 第15-1週 12/30 Ch 16 Sequential Ckt Design (16.1 to 16.4) 第15-2週 12/31 New Year Long Weekend, No Class 第16-1週 1/06 Review Session 第16-2週 1/07 Final Exam (Ch 11-16) 第17-1週 1/13 Supplementary Material [Online] 第17-2週 1/14 Sequential Circuit Design using Altera Quartus II (TA Hour) 第18-1週 1/20 Supplementary Material [Online] 第18-2週 1/21 Supplementary Material [Online]