課程資訊

Switching Circuit and Logic Design

108-1

EE2012

901 32300

03

3.0

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1081SCLD3

Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 11 Latches and FFs
11. Unit 12 Registers and Counters
12. Unit 13 Analysis of Clocked Sequential Circuits
13. Unit 14 Derivation of State Graphs and Tables
14. Unit 15 Reduction of State Tables-- State assignment
15. Unit 16 Sequential Circuit Design

Basic knowledges in Switching Circuits and Logic Design

Quiz 1~4, Quartus II assignment 1 & 2, Midterm, Final

Office Hours

TEXTBOOK
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning.

(僅供參考)

 No. 項目 百分比 說明 1. Quiz 1～4 20% 2. Midterm 35% 3. Quartus II HW 10% 4. Final 35% 學期總成績以等第制給分 原始分數為三班前8%的同學 可以拿到A+

 課程進度
 週次 日期 單元主題 第1-1週 09/12 [交電共同網頁] https://sites.google.com/access.ee.ntu.edu.tw/scld-2019-fall/ [交電本班網頁] https://ceiba.ntu.edu.tw/1081SCLD3 [檔案開啟密碼]1081_ee_scld Chap 1 Introduction, Number Systems 第1-2週 09/13 Moon Festival (no classes) 第2-1週 09/19 [檔案開啟密碼]1081_ee_scld (週四教室之後改為 新204) Chap 1 Introduction, Number Systems; Chap 2 Boolean Algebra 第2-2週 09/20 Chap 2 Boolean Algebra (週五教室之後改為 新103) 第3-1週 09/26 Chap 3 Boolean Algebra (continued) 第3-2週 09/27 Chap 3 Boolean Algebra (continued) 第4-1週 10/03 Quiz 1 (Chap 1~3) 第4-2週 10/04 Chap 4 Applications of Boolean Algebra 第5-1週 10/10 The National Day Long Weekend (no classes) 第5-2週 10/11 The National Day Long Weekend (no classes) 第6-1週 10/17 Chap 5 Karnaugh Maps 第6-2週 10/18 Chap 5 Karnaugh Maps; Chap 7 Multi-Level Gate Circuits, NAND/NOR Gates 第7-1週 10/24 Quiz 2 (Chap 4, 5) 第7-2週 10/25 Chap 8 Combinational Circuit Design (skip Fig 8-12, 8-14) 第8-1週 10/31 Chap 9 Multiplexers Decoders and PLDs 第8-2週 11/01 Chap 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8) **: Shannon’s expansion (Eqs. 9-10~12) will be included in the exam. (no new slides) 第9-1週 11/07 Review Session 第9-2週 11/08 Midterm (Chap 1~5, 7~9) 第10-1週 11/14 Chap 11 Latches and FFs 第10-2週 11/15 University Anniversary (no classes) 第11-1週 11/21 Chap 11 Latches and FFs; Chap 12 Registers and Counters 第11-2週 11/22 Combinational Circuit Design using Altera Quartus II 第12-1週 11/28 Chap 12 Registers and Counters 第12-2週 11/29 Chap 12 Registers and Counters; Chap 13 Analysis of Clocked Sequential Circuits 第13-1週 12/05 Chap 13 Analysis of Clocked Sequential Circuits 第13-2週 12/06 Chap 14 Derivation of State Graphs and Tables 第14-1週 12/12 Quiz 3 (Chap 11, 12) 第14-2週 12/13 Sequential Circuit Design using Altera Quartus II 第15-1週 12/19 Chap 14 Derivation of State Graphs and Tables (Skip Examples 2 & 3 in Sec. 14.3) 第15-2週 12/20 Chap 15 Reduction of State Tables 第16-1週 12/26 Quiz 4 (Chap 13, 14) 第16-2週 12/27 Chap 15 Reduction of State Tables (15.1~15.3); Chap 16 Sequential Circuit Design 第17-1週 01/02 Chap 16 Sequential Circuit Design (16.1~16.4) 第17-2週 01/03 Supplementary Materials 第18-1週 01/09 Review Session 第18-2週 01/10 Final Exam (Chap 11~16)