課程資訊
課程名稱
交換電路與邏輯設計
Switching Circuit and Logic Design 
開課學期
107-1 
授課對象
電機工程學系  
授課教師
江蕙如 
課號
EE2012 
課程識別碼
901E32300 
班次
04 
學分
3.0 
全/半年
半年 
必/選修
必修 
上課時間
星期四8(15:30~16:20)星期五8,9(15:30~17:20) 
上課地點
博理212博理212 
備註
本課程以英語授課。本系優先。
總人數上限:32人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1071EE2012_04 
課程簡介影片
 
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課程概述

Course contest:
Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations  

課程目標
This course offers an introduction to any undergraduate who wants to understand digital systems. This course is essential for later courses in digital design, design automation, computer organization and architecture, logic synthesis and verification, testing and design for testability. 
課程要求
No prerequisites. 
預期每週課後學習時數
 
Office Hours
每週四 14:00~14:30 備註: by appoitment 
參考書目
待補 
指定閱讀
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning. 
評量方式
(僅供參考)
 
No.
項目
百分比
說明
1. 
Homework 
14% 
 
2. 
Quiz 1 
4% 
 
3. 
Midterm 
35% 
 
4. 
Quiz 2 
4% 
 
5. 
Quartus II HW 
6% 
 
6. 
Final 
35% 
 
7. 
Participation 
2% 
 
 
課程進度
週次
日期
單元主題
第1週
9/13,9/14  Ch. 1. Intro, Number Systems 
第2週
9/20,9/21  Ch. 2. Boolean Algebra 
第3週
9/27,9/28  Ch. 3. Boolean Algebra (Continued)  
第4週
10/04,10/05  Ch. 4. Applications of Boolean Algebra 
第5週
10/11,10/12  Ch. 5. Karnaugh Maps /
Ch. 7. Multi-Level Gate Circuits; NAND NOR Gates  
第6週
10/18,10/19  Ch. 7. (cont’d) / Quiz 1 (Ch. 1 ~ Ch. 4) / Ch. 7 (cont’d)  
第7週
10/25,10/26  Ch. 8. Combinational Ckt Design  
第8週
11/01,11/02  Ch. 9. Multiplexers Decoders and PLDs 
第9週
11/08,11/09  Review Session / Midterm (Ch. 1 ~ Ch. 9)  
第10週
11/15,11/16  11/15 No class (NTU Anniversary) / Combinational Circuit Design using Altera Quartus II  
第11週
11/22,11/23  Ch. 11. Latches and FFs / Ch. 12. Registers and Counters  
第12週
11/29,11/30  Ch. 12. (cont’d) / Ch. 13. Analysis of Clocked Sequential Ckts  
第13週
12/06,12/07  Ch. 13. (cont’d) / Sequential Circuit Design using Altera Quartus II  
第14週
12/13,12/14  Ch. 13. (cont’d) / Ch. 14. Derivation of State Graphs and Tables  
第15週
12/20,12/21  Ch. 14. (cont’d) / Quiz 2 (Ch. 11 ~ Ch. 13) / Ch 15. Reduction of State Tables 
第16週
12/27,12/28  Ch. 15. Reduction of State Tables / Ch. 16. Sequential Ckt Design 
第17週
1/03,1/04  Ch. 16. (cont’d) / Supplementary materials  
第18週
1/10,1/11  Review Session / Final Exam (Ch. 11 ~ Ch. 16)