課程資訊

Switching Circuit and Logic Design

104-1

EE2012

901 32300

04

Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1041EE2012_LD04

「交換電路與邏輯設計」課程將介紹如何以「開關」(switch)作為實現布林邏輯與設計數位電路之基本元件，並介紹如何有系統地優化交換電路(switching circuit)。

Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations
Hardware Description Language: Verilog (basics)

Office Hours

C. H. Roth Jr. Fundamentals of Logic Design, 7th Edition, Cengage Learning, 2013

(僅供參考)

 No. 項目 百分比 說明 1. Homework 14% 2. Quiz 1 4% 3. Midterm Exam 35% 4. Quiz 2 4% 5. Project 6% 6. Final Exam 35% 7. Participation 2%

 課程進度
 週次 日期 單元主題 第1週 9/17,9/18 (9/17) §1 Introduction, Number Systems and Conversion (9/18) §1 Introduction, Number Systems and Conversion; §2 Boolean Algebra 第2週 9/24,9/25 (9/24) §2 Boolean Algebra (9/25) §3 Boolean Algebra (Continued) 第3週 10/01,10/02 (10/01) §4 Applications of Boolean Algebra (10/02) §4 Applications of Boolean Algebra 第4週 10/08,10/09 (10/08) §5 Karnaugh Maps (10/09) (No lecture -- Pre-National Day) 第5週 10/15,10/16 (10/15) §5 Karnaugh Maps (10/16) §7 Multi-Level Gate Circuits 第6週 10/22,10/23 (10/22) Quiz (§1 ~ §4) (10/23) §8 Combinational Circuit Design (skip §8.1 and §8.2) 第7週 10/29,10/30 (10/29) [start at 13:20 to make up 11/05 lecture] §8 Combinational Circuit Design (skip §8.1 and §8.2) (10/30) §9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7) 第8週 11/05,11/06 (11/05) (lecture moved to 10/29) [§9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7)] (11/06) Combinational Circuit Design Using Altera Quartus II (held by TA) 第9週 11/12,11/13 (11/12) Review Session (11/13) Midterm Exam (§1~§9) 第10週 11/19,11/20 (11/19) §11 Latches and Flip-Flops (11/20) §11 Latches and Flip-Flops 第11週 11/26,11/27 (11/26) §12 Registers and Counters (11/27) §12 Registers and Counters 第12週 12/03,12/04 (12/03) §13 Analysis of Clocked Sequential Circuits (12/04) §13 Analysis of Clocked Sequential Circuits 第13週 12/10,12/11 (12/10) §14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3) (12/11) §15 Reduction of State Tables (§15.1 ~ §15.3) 第14週 12/17,12/18 (12/17) Quiz 2 (§11 ~ §13) (12/18) Sequential Circuit Design Using Altera Quartus II (held by TA) 第15週 12/24,12/25 (12/24) §16 Sequential Circuit Design (§16.1 ~ §16.4) (12/25) §16 Sequential Circuit Design (§16.1 ~ §16.4) 第16週 12/31,1/01 (12/31) §16 Sequential Circuit Design (§16.1 ~ §16.4) (01/01) (no lecture -- Happy New Year!) 第17週 1/07,1/08 (01/07) Presentation of Selected Projects [start at 13:20] (01/08) Supplementary Materials 第18週 1/14,1/15 (01/14) Review Session (01/15) Final Exam