課程資訊
課程名稱
數位系統設計
Digital System Design 
開課學期
107-2 
授課對象
電機資訊學院  電機工程學系  
授課教師
吳安宇 
課號
EE4041 
課程識別碼
901 43500 
班次
 
學分
3.0 
全/半年
半年 
必/選修
選修 
上課時間
星期四7,8,9(14:20~17:20) 
上課地點
電二144 
備註
總人數上限:40人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1072_DSD 
課程簡介影片
 
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課程概述

Digital System Design Introduction
Fundamentals of Hardware Description Language
Logic Design at Register Transfer Level
Logic Design with Behavior Coding, Design Validation
Synthesizable Coding of Verilog
Coding Style and Verification Tool
Synthesis Tool Usage
Complexity Management and Performance Improvement
Implementation Project: MIPS Processor 

課程目標
Basics:
Basic overview of digital systems
Front-end cell-based design flow, theory & practice
Refinement and improvement issues for digital systems

Presentation:
Implementation project
Peer competetion for advanced design features
Oral presentation 
課程要求
Prerequisite:
Switch circuits and logic designs
Electronics

Grading:
Homework: 30% (HW1:5% HW2:5% HW3:10% HW4: 10%)
Midterm Exam: 30%
Machine Test: 5%
Final Project: 30%
Impression: 5% (Attendance/Attitude)
 
預期每週課後學習時數
 
Office Hours
 
參考書目
Slides in courses are the main materials

Related textbooks can be referred to:
“Verilog HDL: Digital design and modeling,” Joseph Cavanagh, CRC Press, 2007.
“Computer organization and design: The hardware/software interface,” David A.
Patterson and John L. Hennessy, 2014, 5th Edition.
“Computer organization and design: The hardware/software interface,” David A.
Patterson and John L. Hennessy, RISC-V Edition.
“Digital system designs and practices: Using Verilog HDL and FPGAs," Ming-Bo Lin,
Wiley, 2008.
 
指定閱讀
待補 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
第7週
4/04  Spring Break 
第11週
5/02  Midterm 
第12週
5/09  Cache and Memory Hierarchy  
第13週
5/16  Pipeline MIPS

Slide is on CEIBA (with class Passcode) 
第15週
5/30  Machine Test 
第16週
6/06  Project Check Point