The intention of this course is two fold: (1) Give the device-oriented students a comprehensive picture of the scaling limit and the future direction beyond the scaling limit based on physics, technologies, and market demand. Hopefully, the young talent can pass the red brick wall after the inspiration. (2) Give the circuit-oriented students a comprehensive understanding of the device physics, and the characteristics of the next generation devices. Hopefully, the designers can know the physics not modeled by the SPICE and to be taken into account for the circuit design. The technology generation can be transparent for the proper circuit design. The device knowledge is essential for analog , RF circuit design, and reliability.
The content will be taught in three major areas:
(1) The device physics which determines the speed and power trade-off in terms of supply voltage and threshold voltage (see figures, Science vol. 306, p.2057, 2004) based on the scaling of classical MOSFET.
(2) The mobility enhancement, high K and metal gate for CMOS, the multi-gate SOI devices such as Fin FET, tri-gate device, and innovative devices such as I-MOS.
(3) Circuit implication for next generation technology if there is a need.
If most student are not familiar with CMOSFET, some basics will be covered in the beginning lectures.
Text book: The fundament of device physics (Y. Taur and T. Ning): CMOS part
Reference: IEEE IEDM, EDL, ED and nanotechnology, handout will be downloaded in website (to be announced)
Grading: midterm, final, homework, and term project (very important)
The student who will not dedicate themselves to the Si industry or academic research should not take course.