課程資訊
課程名稱
通訊積體電路設計
Design of Communication Integrated Circuits 
開課學期
106-2 
授課對象
電機資訊學院  生醫電子與資訊學研究所  
授課教師
李致毅 
課號
EE5036 
課程識別碼
921 U1560 
班次
 
學分
3.0 
全/半年
半年 
必/選修
選修 
上課時間
星期五2,3,4(9:10~12:10) 
上課地點
電二106 
備註
總人數上限:100人 
 
課程簡介影片
 
核心能力關聯
本課程尚未建立核心能力關連
課程大綱
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課程概述

I. Introduction
II. System-on-Chip Design Methodology
III. Signal Processing Fundamentals (*)
IV. System/Architecture Designs
V. Device Models and Technologies
VI. Linear Basic Circuits (review)
VII. Analog Front End Circuits
VIII. Analog Rear End Circuits
IX. Non-linear Circuits
X. Low-Voltage Low-Power Circuit Design Techniques 

課程目標
This course deals with the design and analysis of linear and non-linear integrated circuits for communi-cation system VLSIs using Bipolar, MOS and BiCMOS technologies: operational amplifiers, wideband amplifiers; analog-digital/digital-analog converters; filters; variable gain amplifier; mixer; phase detector ; oscillator ; and use of these circuit design techniques in sub-systems/systems such as constant magnitude control and timing recovery. 
課程要求
1.grading

Problem Sets: 15%
Midterms: 20% @ 9th. Week
Final: 40% @ 18th. Week
Term Project: 25%

◆ Assignments
a. Home Works
There will be approximately 8 homework assignments.
b. Term Project
There will be one non-linear circuit design project.


2.prerequisite:

Introductory course in Electronics ( familiar with principles of transistor operation , and functioning ) ; Laplace Transform ; Frequency-domain circuit analysis ; Network and filters ; Linear and non-linear circuits and systems; Digital signal processing ; Simulation in e.g. Spice.
 
預期每週課後學習時數
 
Office Hours
 
參考書目
Textbook: Handouts and Papers
Reference:
[1]"Analysis and Design of Analog Integrated Circuits," P. R. Gray, P. Hurst. S. Lewis and R. G. Meyer John Wiley & Sons, 2001

[2]"Phase Lock Loops" from "The VLSI Handbook," M. S. Yuan and C. K. Wang
IEEE Press, (1999)

[3]"Phase-Locked Loops," Roland. E. Best, McGraw-Hill, 1993 
指定閱讀
 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
無資料