B. Course Contents: This course focuses on the physical design for the nanometer process technology.
1. Introduction to modern VLSI design flow, design styles, and technology roadmap
2. Circuit partitioning (iterative improvement algorithms, network-flow based algorithm, simulated annealing based approach, multilevel partitioning)
3. Floorplanning (floorplan representations, simulated annealing based algorithms, integer programming based algorithms, partition-based algorithms, analytical algorithms)
4. Placement (linear assignment, min-cut algorithm, force-directed method, quadratic placement, mixed-size placement)
5. Global routing (maze routing, line-search algorithms, stenier-tree based algorithms)
6. Detailed routing (channel routing, switchbox routing, over-the-cell routing, full-chip routing)
7. Clock-tree synthesis (RC delay model, matching based algorithms, zero-skew clock routing, DME clock routing, mathematical programming based algorithms)
8. Performance-driven post-layout optimization
9. Large-scale circuit partitioning, floorplanning, placement, and routing (hierarchical and multilevel frameworks)
10. Signal, power, and thermal integrity (noise modeling, crosstalk minimization, signal simulation, power/ground network design, thermal optimization)
11. Design for manufacturing (process variation modeling, metal-fill patterning for CMP, optical proximity correction, phase-shift mask)
12. Design convergence/timing closure (interconnect-driven design flow, interconnect-driven floorplanning, wiring planning, buffer block planning)
1. Sait and Youssef, VLSI Physical Design Automation, World Scientific/IEEE Press, 1999.
2. Selected recent publications on physical design for nanometer ICs.
1. Homework assignments 25%
2. Two programming assignments 25%
3. One in-class test 30%.
4. Project 20%
E. Prerequisites: logic design and at least one course in data structures/discrete mathematics/algorithms