本課程係以電機系所與電子所,大四及研究生為對象,每週三堂課,為選修課程,三學分的課程。
使用教材以課堂講義為主,相關書籍為輔,共分為九部分。內容包括
1. Analysis of the Phase-locked Loops
2. Building Blocks in PLLs
3. Phase noise and jitter
4.The architectures of PLLs :
Integer and Fractional-N synthesizers
Clock/Data Recovery circuits
5. Case Studies for PLLs
6. Analysis of Delay locked loops(DLLs)
7. Design issues in DLLs
8. The architectures of DLLs
9. Case Studies for DLLs
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