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課程名稱 |
高等計算機結構
Advanced Computer Architecture |
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開課學期 |
105-2 |
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授課對象 |
電機資訊學院 資訊網路與多媒體研究所 |
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授課教師 |
楊佳玲 |
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課號 |
CSIE5059 |
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課程識別碼 |
922 U1470 |
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班次 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期二7,8,9(14:20~17:20) |
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上課地點 |
資310 |
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備註 |
總人數上限：30人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1052CSIE5059_ |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Computer architecture has evolved — from a world of mainframes, minicomputers, and microprocessors, to a world dominated by microprocessors, and now into a world where microprocessors themselves are encompassing all the complexity of mainframe computers. |
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課程目標 |
This course focuses on advanced computer architecture design such as deep pipelining, techniques to exploit instruction level parallelism and thread level parallelism, and memory hierarchy management.
Students will acquire the skills of evaluating the performance of alternative design choices in system design. |
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課程要求 |
待補 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
待補 |
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參考書目 |
Textbook & Reference Books:
(1) Computer Architecture: A Quantitative Approach. 5th Edition, John L.
Hennessy and David A. Patterson, Morgan, 20011
(2) Selected papers |
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評量方式
(僅供參考) |
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週次 |
日期 |
單元主題 |
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第1週 |
2/21 |
Course Introduction |
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第2週 |
2/28 |
228放假 |
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第3週 |
3/07 |
Basics of Computer Architecture Design
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第4週 |
3/14 |
Instruction-Level Parallelism   |
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第5週 |
3/21 |
Memory Hierarchy: Cache & DRAM Architecture |
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第6週 |
3/28 |
Parallel architecture |
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第7週 |
4/04 |
No class |
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第8週 |
4/11 |
Paper presentation I : DRAM optimization
1. 沈恩禾: A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM (ISCA'12)
2. 姜博允: Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning (MICRO'11)
3. 林孟瑤: CREAM: A Concurrent-Refresh-Aware DRAM Memory System (HPCA'14) |
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第9週 |
4/18 |
Midterm Exam |
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第10週 |
4/25 |
Data-level parallelism/
Term project announcement |
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第11週 |
5/02 |
[Lecture]
Low-power architecture |
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第12週 |
5/09 |
[Lecture]
warehouse computing |
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第13週 |
5/16 |
Paper Presentation II: GPU
1. 陳永傑: Divergence-Aware Warp Scheduling (MICRO'13)
2. 柯志霖: Warped Register File: A Power Efficient Register File for GPGPUs (HPCA'13)
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第14週 |
5/23 |
Paper Presentation III: Storage architecture
1. 江懿友: On the Performance Variation in Modern Storage Stacks (FAST'17)
2. 趙一穎: To FUSE or Not to FUSE: Performance of User-Space File Systems (FAST'17) |
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第15週 |
5/30 |
端午節放假 |
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第16週 |
6/06 |
Paper Presentation IV: Accelerator Design
1. 陳貽祥: Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures (ISCA'14)
2. 陳啟中: Supporting Address Translation for Accelerator-Centric Architectures (HPCA'17)
3. 吳奕亨: Minerva: Enabling Low-Power, High-Accuracy Deep Neural Network Accelerators (ISCA'16)
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第17週 |
6/13 |
Project Presentation |
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