COURSE CONTENTS:
AS TECHNOLOGY CONTINUES TO SCALE, POWER HAS THE FIRST-ORDER DESIGN ISSUE.
THIS COURSE COVERS THE LATEST DEVELOPMENT AT ARCHITECTURAL-LEVEL AND
SYSTEM-LEVEL POWER REDUCTION TECHNIQUES, INCLUDING LOW-POWER PROCESSOR
DESIGN, LOW-POWER INTERCONNECTION, DYNAMIC POWER MANAGEMENT, LOW-POWER FLASH
STORAGE, AND POWER/THERMAL ISSUES IN CMP ARCHITECTURE. STUDENTS WILL ACQUIRE
THE SKILLS OF EVALUATING THE POWER OF ALTERNATIVE DESIGN CHOICES IN SYSTEM
DESIGN, AND SOFTWARE OPTIMIZATION FOR ENERGY EFFICIENCY.

COURSE OUTLINE:
A.. COURSE INTRODUCTION
B.. BASICS OF POWER CONSUMPTION
A.. DYNAMIC POWER VS. LEAKAGE POWER
B.. ARCHITECTURAL-LEVEL POWER MODELING
C.. WATTCH TOOL SET
C.. LOW-POWER PROCESSOR DESIGN
A.. POWER GATING, CLOCK GATING, DVS TECHNIQUES
B.. LOWER-POWER CACHE ARCHITECTURE
D.. CASE STUDY — ANDES PROCESSOR
E.. LOW-POWER INTERCONNECTION DESIGN
A.. BUS ENCODING SCHEMES
B.. ENERGY-AWARE NOC (NETWORK-ON-CHIP) DESIGN
F.. SYSTEM-WIDE POWER MANAGEMENT
A.. DYNAMIC POWER MANAGEMENT (DPM) FOR PERIPHERALS
G.. LOW-POWER FLASH STORAGE SYSTEM
H.. THERMAL-AWARE ARCHITECTURE DESIGN
A.. THERMAL-AWARE ARCHITECTURAL-LEVEL FLOORPLANNING
B.. DTM (DYNAMIC THERMAL MANAGEMENT)
I.. POWER/THERMAL ISSUES IN CMP