===== Announcement on the online lecture =======================
For those who are interested in auditing the course, you can participate in the online lecture by
1. Send email to r08943134@ntu.edu.tw
2. Due to limited lab equipment, the couse does not have second enrollment.
3. The first lecture online course Google meeting link below:
Application Acceleration with High-Level-Synthesis Online Course
9月 27日 (星期一) · 上午9:10 - 下午12:10
Google Meet 会议加入信息
视频通话链接：https://meet.google.com/ifb-twqn-xci
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The course includes lectures, laboratories, and a final project. The class lectures will be in English. Lecture includes but is not limited, the following subjects,
1. Tools & Platform
a. Introduction to PYNQ & Lab2
b. Vitis OpenCL XRT and Lab3
2. Basic Design Concept and HLS
a. From Logic Gate to HLS
b. Introduction to High-Level Synthesis
3. FPGA (Xilinx)
a. Introduction to FPGA
b. FPGA – CLB
c. FPGA – Memory
d. FPGA – DSP
e. FPGA – Interconnect
4. Concept of System Performance and Optimization
a. System Performance - Host
b. System Performance - Kernel
5. Coding Style
a. Sequential and Combinatorial Hardware
b. Memory Architecture
c. Hierarchical Design
6. HLS Optimization Techniques
a. Introduction to High-Level Synthesis
b. Kernel IO Interface
c. Kernel Optimization – Array
d. Kernel Optimization – Latency
e. Kernel Optimization – Pipeline
7. Special Topics
a. From AI to Gate
b. HLS RISC-V
c. Arithmetic Trading
8. Design Examples and Application
a. Design Examples
b. Application Cases
Lab/Project Resources
• 3 Basic Labs
-Lab#1 – Tools Installation and implementation flow, includingVivado-HLS, Vivado Design Suite, Vitis IDE/Makefile, PYNQ-Z2
- Lab#2 – Application Acceleration for Embedded System – PYNQ-Z2
- Lab#3 – Application Acceleration for Cloud Environment – U50 with Vitis & XRT
• Lab#A - ug871
- Lab#B - Vitis Library
- Lab#C - From AI to Gate
• Final Projects