課程資訊
課程名稱
高階合成技術於應用加速
Application Acceleration with High-Level-Synthesis 
開課學期
111-1 
授課對象
電機資訊學院  電子工程學研究所  
授課教師
賴瑾 
課號
EEE5060 
課程識別碼
943 U0620 
班次
 
學分
3.0 
全/半年
半年 
必/選修
選修 
上課時間
星期四7,8,9(14:20~17:20) 
上課地點
電二144 
備註
總人數上限:30人 
 
課程簡介影片
 
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課程概述

本課程的目標是使軟件/硬件設計人員能夠開發高效的硬件加速器,並進一步開發一種以有效方式集成應用程序和硬件加速器的系統。
本課程分為兩個部分。第一部分是提供開發C / C ++代碼的技能,該代碼可以有效地轉換為硬件。它從邏輯設計,FPGA架構,使用Pynq-Z2板,EDA工具,了解高級綜合的內部工作流程,C / CC +到RTL映射,設計分析和優化的背景開始。逐步說明示例。有大量的實驗工作和作業,以給學生實踐經驗。學期結束前,將舉行一系列有關最終項目的研討會介紹。
第二部分是探索硬件軟件的協同設計。通過探討各種體系結構問題,從高級主題高級綜合開始。通過探索性能瓶頸,工作分區,設計有效的通信協議和運算核心開發來實踐軟件-硬件協作的過程。憑藉所學的技能,團隊中的學生將研究一個學期項目來解決實際應用,示例應用包括數據庫,生物信息學,財務,機器學習等。學期項目將產生各種硬件-軟件協同設計問題被討論。該過程就像從計劃到成功交付解決方案來開發真正的嵌入式產品。

===== Announcement on the online lecture =======================
For those who are interested in auditing the course, you can participate in the online lecture by
1. Send email to wilbur@access.ee.ntu.edu.tw
2. The first lecture online course Google meeting link below:
Application Acceleration with High-Level Synthesis
Thursday, September 8 · 2:00 – 5:30pm
Google Meet joining info
Video call link: https://meet.google.com/avt-bfeu-kjf
Or dial: ‪(US) +1 252-820-1278‬ PIN: ‪233 097 836‬#
More phone numbers: https://tel.meet/avt-bfeu-kjf?pin=7279226732258

=====================================
The course includes lectures, laboratories, and a final project. Lecture includes but is not limited, the following subjects,
1. Tools & Platform
a. Introduction to PYNQ and Lab2
b. Vitis OpenCL XRT and Lab3
c. Vitis Development Flow
2. Basic Design Concept and HLS
a. From Logic Gate to HLS
b. Introduction to High-Level Synthesis
3. FPGA (Xilinx)
a. Introduction to FPGA
b. FPGA – CLB
c. FPGA – Memory
d. FPGA – DSP
e. FPGA – Interconnect
4. Kernel Optimization
a. Kernel IO Interface
b. Pipeline
c. Dataflow
5. Structure Design & Hierarchical Design
6. Advanced Topics
a. Memory Architecture
b. Application Acceleration Best Practice
c. Architecture Design Examples
Lab/Project Resources
‧ 3 Basic Labs
- Lab#1 – Tools Installation and implementation flow, includingVivado-HLS, Vivado Design Suite, Vitis IDE/Makefile, PYNQ-Z2
- Lab#2 – Application Acceleration for Embedded System – PYNQ-Z2
- Lab#3 – Application Acceleration for Cloud Environment – U50 with Vitis and XRT
. Labs for Design analysis, algorithm accelerator
- Lab#A - Design flow and tool
- Lab#B - Algorithm accelerator examples
- Lab#C - Advanced
‧ Final Projects
 

課程目標
Upon completion of the course, students will be able to (1) use HLS tools to design complex digital circuits (2) Independently analyze and optimize the design (3) Independently research on the specific application area, evaluate and use the open-source resources to develop end-to-end application acceleration (4) Collaborate with other members in a small team to develop a solution for application acceleration. 
課程要求
‧ Knowledge of C/C++
‧ Basic concept of logic design, computer architecture
‧ Knowledge of basic algorithms, and data structures
‧ Experiences with RTL design for ASIC or FPGA would be helpful, but not required 
預期每週課後學習時數
 
Office Hours
備註: Up request! 
參考書目

‧ HLS Textbook: https://www.boledu.org/textbooks/hls-textbook
. R. Kastner, J. Matai, and S. Neuendorffer, Parallel Programming for FPGAs https://github.com/KastnerRG/pp4fpgas/raw/gh-pages/main.pdf
‧ Xilinx ug1399 Vitis High-Level Synthesis User Guide: https://docs.xilinx.com/r/en-US/ug1399-vitis-hls
. Xilinx ug902: Vivado Design Suite User Guide: High-Level Synthesis, https://bit.ly/3x4r8mp
. Xilinx ug871: Vivado Design Suite Tutorial: High-Level Synthesis, https://bit.ly/3v1KtTg
 
指定閱讀
待補 
評量方式
(僅供參考)
   
針對學生困難提供學生調整方式
 
上課形式
以錄影輔助
作業繳交方式
考試形式
其他
課程進度
週次
日期
單元主題
第1週
9/08  Application Acceleration with High-Level Synthesis - An Industrial Perspective
HLS Introduction & Course Plan
From Logic Gate to HLS 
第2週
9/15  Introduction PYNQ & Lab2
Introduction to HLS 
第3週
9/22  Vitis OpenCL XRT and Lab3
Vitis Development Flow 
第4週
9/29  Kernel IO Interface
Introduction to FPGA - CLB, Memory, DSP, Interconnect 
第5週
10/06  Kernel Optimization - Pipeline
Kernel Optimization - Dataflow 
第6週
10/13  Presentation Lab#A (individual) 
第7週
10/20  Structure Design
Hierarchical Design 
第8週
10/27  Presentation Lab#B (individual) 
第9週
11/03  Data Type - Midterm Exam 
第10週
11/10  FINN 
第11週
11/17  Presentation Lab#C (Team) 
第12週
11/24  Memory Architecture 
第13週
12/01  Final Project Proposal Presentation (Team) 
第14週
12/08  Application Acceleration Best Practice 
第15週
12/15  Application Acceleration Architecture Design Examples 
第16週
12/22  Final Exam Week (No Class) 
第17週
12/29  Final Project Presentation