課程資訊
課程名稱
高階合成技術於應用加速
Application Acceleration with High-Level-Synthesis 
開課學期
110-1 
授課對象
電機資訊學院  電子工程學研究所  
授課教師
賴瑾 
課號
EEE5060 
課程識別碼
943EU0620 
班次
 
學分
3.0 
全/半年
半年 
必/選修
選修 
上課時間
星期一2,3,4(9:10~12:10) 
上課地點
博理114 
備註
本課程以英語授課。
總人數上限:59人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1101EEE5060_ 
課程簡介影片
 
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課程概述

===== Announcement on the online lecture =======================
For those who are interested in auditing the course, you can participate in the online lecture by
1. Send email to r08943134@ntu.edu.tw
2. Due to limited lab equipment, the couse does not have second enrollment.
3. The first lecture online course Google meeting link below:
Application Acceleration with High-Level-Synthesis Online Course
9月 27日 (星期一) · 上午9:10 - 下午12:10
Google Meet 会议加入信息
视频通话链接:https://meet.google.com/ifb-twqn-xci
=====================================

The course includes lectures, laboratories, and a final project. The class lectures will be in English. Lecture includes but is not limited, the following subjects,
1. Tools & Platform
a. Introduction to PYNQ & Lab2
b. Vitis OpenCL XRT and Lab3
2. Basic Design Concept and HLS
a. From Logic Gate to HLS
b. Introduction to High-Level Synthesis
3. FPGA (Xilinx)
a. Introduction to FPGA
b. FPGA – CLB
c. FPGA – Memory
d. FPGA – DSP
e. FPGA – Interconnect
4. Concept of System Performance and Optimization
a. System Performance - Host
b. System Performance - Kernel
5. Coding Style
a. Sequential and Combinatorial Hardware
b. Memory Architecture
c. Hierarchical Design
6. HLS Optimization Techniques
a. Introduction to High-Level Synthesis
b. Kernel IO Interface
c. Kernel Optimization – Array
d. Kernel Optimization – Latency
e. Kernel Optimization – Pipeline
7. Special Topics
a. From AI to Gate
b. HLS RISC-V
c. Arithmetic Trading
8. Design Examples and Application
a. Design Examples
b. Application Cases
Lab/Project Resources
• 3 Basic Labs
-Lab#1 – Tools Installation and implementation flow, includingVivado-HLS, Vivado Design Suite, Vitis IDE/Makefile, PYNQ-Z2
- Lab#2 – Application Acceleration for Embedded System – PYNQ-Z2
- Lab#3 – Application Acceleration for Cloud Environment – U50 with Vitis & XRT
• Lab#A - ug871
- Lab#B - Vitis Library
- Lab#C - From AI to Gate
• Final Projects 

課程目標
Upon completion of the course, students will be able to (1) use HLS tools to design complex digital circuits (2) Independently analyze and optimize the design (3) Independently research on the specific application area, evaluate and use the open-source resources to develop end-to-end application acceleration (4) Collaborate with other members in a small team to develop a solution for application acceleration. 
課程要求
• Knowledge of C/C++
• Basic concept of logic design, computer architecture
• Knowledge of basic algorithms, and data structures
• Experiences with RTL design for ASIC or FPGA would be helpful, but not required
 
預期每週課後學習時數
 
Office Hours
 
參考書目
• R. Kastner, J. Matai, and S. Neuendorffer, Parallel Programming for FPGAs
• Mentor HLS Bluebook
• Xilinx ug902: Vivado Design Suite User Guide: High-Level Synthesis,
• Xilinx ug871: Vivado Design Suite Tutorial: High-Level Synthesis,
 
指定閱讀
• Reference Papers (listed in each ppt)
• Manual/Datasheets (listed in each ppt)
• Selected chapters from books (listed in each ppt)
 
評量方式
(僅供參考)
   
課程進度
週次
日期
單元主題
第1週
9/27  HLS Introduction and Course Plan
From Logic Gate to HLS
PYNQ Introduction and Lab2
Assignment: Lab1 - Tool Installation
Assignment: Lab2 - HLS on PYNQ 
第2週
10/04  HLS Development Flow
Vitis OpenCL XRT and Lab3
Introduction to HLS
Assignment: Lab3 - HLS on U50 (1w) 
第3週
10/11  休課-國慶日補假
Assignment: Lab#A - ug871 (2w) 
第4週
10/18  Introduction to FPGA - CLB, Memory, DSP, Interconnect
Kernel IO Interface 
第5週
10/25  Kernel Optimization - Pipeline
Kernel Optimization - Dataflow
Assignment: Lab#B - Vitis Library - team (4w) 
第6週
11/1  Host Optimization
Kernel Optimization - Area, Latency, Throughput
Selected LAB#A Presentation 
第7週
11/08  Structure Design
Hierarchical Design 
第8週
11/15  Midterm  
第9週
11/22  Presentation - Lab#B 
第10週
11/29  From AI to Gate
Assignment - Lab#C - From AI to Gate 
第11週
12/06  From AI to Gate
Assignment - Research on Final Project Proposal 
第12週
12/13  HLS Applications 
第13週
12/20  Memory Architecture
Design Example 
第14週
12/27  Presentation - Final Project Proposal 
第15週
1/3  Selected HLS micro-architecture design
Application Examples 
第16週
1/10  休課 - 無期末考 
第17週
1/17  休課 
第18週
1/24  Final Project Presentation