課程名稱 |
系統晶片設計實驗 Soc Design Laboratory |
開課學期 |
112-1 |
授課對象 |
電機資訊學院 電子工程學研究所 |
授課教師 |
賴 瑾 |
課號 |
EEE5010 |
課程識別碼 |
943 U0100 |
班次 |
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學分 |
3.0 |
全/半年 |
半年 |
必/選修 |
選修 |
上課時間 |
星期四7,8,9(14:20~17:20) |
上課地點 |
電二101 |
備註 |
總人數上限:30人 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
課程大綱
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課程概述 |
This course is the first part of two-semester SOC Design Course. The course starts with basic design skill (Verilog/HLS), study SOC architecture, and finally design an IP to integrate in SOC.
The laboratories are based on Caravel SOC running in PYNQ FPGA. You will also develop embedded program runs in both Caravel/RISCV and FPGA/ARM processor.
The course equips participants with the skills and knowledge required to become full-stack IC designers, able to handle all development stages from front-end design to system debugging and embedded programming. |
課程目標 |
Upon completion of the course, students will be able
1. Learn Verilog and HLS Design Implementation on FPGA and ASIC
2. Implement an IP and Integrate it into a SOC design
3. Realize the SOC design and emulate it in FPGA
4. Labs based on CaravelFPGA |
課程要求 |
• Knowledge of C/C++
• Basic concept of logic design, computer architecture
• Experiences with RTL design for ASIC or FPGA would be helpful, but not required |
預期每週課後學習時數 |
It is expected at 5-10 hours of off-class lab work and study time, depending on background. |
Office Hours |
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指定閱讀 |
NA |
參考書目 |
Reference material is listed in each ppt for further reading.
• Reference Manuals on EDA tools (Simulator, Synthesis, Static Timing Analysis)
• Verilog manuals, Lint reference
• Xilinx MPSOC Technical Reference Manual
• Github Caravel https://caravel-harness.readthedocs.io/en/latest/ |
評量方式 (僅供參考) |
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針對學生困難提供學生調整方式 |
上課形式 |
以錄音輔助 |
作業繳交方式 |
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考試形式 |
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其他 |
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週次 |
日期 |
單元主題 |
Week 0 |
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The following content will be scheduled in the semester.
Lectures on Design
1. Introduction to HLS and tools
2. VLSI Circuit Basics
3. Logic Design
4. Structure Design with HLS and Verilog
5. HLS pipeline, dataflow, datatype
6. Verification
7. Introduction to FPGA and its architecture
8. SOC module level specification & Design
9. Embedded Programming – 1st part
Design Flow
1. Tools – Tcl, Perl, Makefile
2. Simulator - Verilog, Coverage, assertion
3. Synthesis
4. Timing analysis
5. Verification Methodology
Laboratories
1. Vitis/Vivado Tool Installation
2. Lab#1 - FIR Filter (AXI master, AXI Stream)
3. Caravel SOC Simulation Environment
4. HLS - Design Analysis & Optimization
5. HLS/Verilog Lab
6. Caravel SOC FPGA Implementation
7. User IP Integration with Caravel SOC
8. Final Project
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Week 1 |
9/7 |
Course plan
Lab#1 - Tool installation - iverilog/gtkwave , gcd example |
Week 2 |
9/14 |
HLS
Lab#2 - HLS FIR (stream/master) Observe Axilite, Axis, Axim + ILA |
Week 3 |
9/21 |
Verilog
Lab#3- Verilog FIR using XSIM & GTKWave (2w) |
Week 4 |
9/28 |
No Class |
Week 5 |
10/5 |
Caravel SoC System
Lab#4-1 Caravel SOC - Management FW (1w) - team |
Week 6 |
10/12 |
Computer & Microprocessor Architecture - RISC-V
Lab#4-2 Caravel User Project - FIR (1w) - team |
Week 7 |
10/19 |
SoC Peripherals - UART, SPI, I2C, GPIO, UserProject IO, DMA
Lab#5 - Caravel FPGA (2w) - team |
Week 8 |
10/26 |
SOC Interconnect (Wishbone, AXI, Switch, DMA) |
Week 9 |
11/2 |
Caravel SOC Lab Presentation - Caravel SOC design/FW, FIR
Lab#A-D team (3w) |
Week 10 |
11/9 |
SOC Memory - Cache/DDR |
Week 11 |
11/16 |
Midterm |
Week 12 |
11/23 |
Embedded Programming - I (ISA, Interrupt, Debugging)
Lab#6 & Final Project - WLOS (4-6 w) |
Week 13 |
11/30 |
Static Timing Analysis & Optimization - BASIC |
Week 14 |
12/7 |
Caravel SOC Lab Presentation - Caravel FPGA & Lab#A-D |
Week 15 |
12/14 |
Synthesis/Scripting |
Week 16 |
12/21 |
Verification & Simulation |
Week 17 |
12/28 |
Final Project Presentation |
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