課程名稱 |
邏輯合成與驗證 Logic Synthesis and Verification |
開課學期 |
109-1 |
授課對象 |
電機資訊學院 電子工程學研究所 |
授課教師 |
江介宏 |
課號 |
EEE5028 |
課程識別碼 |
943EU0300 |
班次 |
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學分 |
3.0 |
全/半年 |
半年 |
必/選修 |
選修 |
上課時間 |
星期三2,3,4(9:10~12:10) |
上課地點 |
電二145 |
備註 |
本課程以英語授課。 總人數上限:20人 |
Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1091_lsv |
課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
課程大綱
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課程概述 |
Logic synthesis is an automated process of generating logic circuits satisfying certain Boolean constraints and/or transforming logic circuits with respect to optimization objectives. It is an essential step in the design automation of VLSI systems and is crucial in extending the scalability of formal verification tools. This course introduces classic logic synthesis problems and solutions as well as some recent developments. |
課程目標 |
This course is intended to introduce Boolean algebra, Boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. The students may learn useful Boolean reasoning techniques for various applications even beyond logic synthesis. |
課程要求 |
The prerequisite is the undergrad "Logic Design" course. Knowledge about data structures and programming would be helpful. |
預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
待補 |
參考書目 |
* F. M. Brown. Boolean Reasoning: The Logic of Boolean Equations. Dover, 2003.
* S. Hassoun and T. Sasao. Logic Synthesis and Verification. Springer, 2001.
* G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Springer, 2006.
* W. Kunz and D. Stoffel. Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques. Springer, 1997.
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評量方式 (僅供參考) |
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週次 |
日期 |
單元主題 |
第1週 |
09/16 |
Introduction; ABC Tutorial |
第2週 |
09/23 |
Boolean Algebra |
第3週 |
09/30 |
Representations of Boolean Functions |
第4週 |
10/07 |
Representations of Boolean Functions |
第5週 |
10/14 |
SOPs and Incompletely Specified Functions |
第6週 |
10/21 |
SOPs and Incompletely Specified Functions |
第7週 |
10/28 |
Two-Level Logic Minimization (1/2) |
第8週 |
11/04 |
Two-Level Logic Minimization (2/2) |
第9週 |
11/11 |
Midterm Exam |
第10週 |
11/18 |
Multi-Level Logic Minimization (1/2) |
第11週 |
11/25 |
Multi-Level Logic Minimization (2/2) |
第12週 |
12/02 |
Logic Flexibility |
第13週 |
12/09 |
Technology Mapping |
第14週 |
12/16 |
Timing Analysis and Optimization |
第15週 |
12/23 |
Sequential Circuit Optimization |
第16週 |
12/30 |
Reversible and Quantum Circuit Synthesis |
第17週 |
01/06 |
Equivalence and Property Verification |
第18週 |
01/13 |
Final Quiz; Project Presentation |
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